1. Technical Field
The present invention relates to semiconductor devices and, in particular, to a semiconductor device having a through electrode formed therein, a circuit substrate incorporating the semiconductor device, and an electronic device incorporating the semiconductor device.
2. Related Art
Electronic information devices, as typified by cellular telephones, have become more compact and lighter, and the function thereof has become more sophisticated and faster. As a result, the IC which is the heart of such a device is also required to achieve miniaturization and weight reduction and to have more sophisticated function, and it is necessary to increase the added value thereof including shorter TAT (turn around time) and cost reduction.
Generally, it requires time and cost to commercialize what is called a system LSI. In addition, a region where a device element such as a SAW (surface acoustic wave) element and an IC are mounted together has also become smaller and lighter, making it difficult to meet systematization.
The existing system packaging technique has used the wire bonding technique to lay chips one on top of another three-dimensionally, thereby reducing the footprint, making the package lighter and more compact, and achieving sophisticated function. However, it has been believed that the dependence on the wire bonding technique makes it difficult to achieve further miniaturization, weight reduction, and more sophisticated function.
Under these circumstances, in recent years, a through hole has been formed in a silicon substrate forming an IC by a technique called TSV (through Si via), and a through electrode has been formed by using the through hole. By doing so, the wiring distance in obtaining electrical continuity between the multilayer chips is minimized, whereby the system package is made lighter and more compact.
As for TSV, various techniques have been disclosed as described in Japanese Patent No. 3,879,816, Japanese Patent No. 3,970,211, JP-A-2007-311584 and JP-A-2006-128172 (Patent Documents 1 to 4). For example, in the technique disclosed in Patent Document 1, a depression is formed on the surface of a Si substrate by dry etching, a through hole is formed by a laser beam, and an intermediate part of the through hole is widened by wet etching.
Moreover, Patent Document 2 describes that, when a through hole is formed from the front surface of a Si substrate by a laser beam or dry etching, the side wall of the through hole is formed in a tapered shape so that an opening area is decreased from an opening on one surface to an opening on the other surface in order to make it easy to form an insulation film.
In addition, Patent Document 3 describes that the side wall of a through hole is formed perpendicularly by forming the through hole in a Si substrate by using the Bosch process.
Furthermore, Patent Document 4 describes that poor connection due to deformation of an electrode pad associated with distortion caused by the formation of a through hole is prevented by making the width of the bottom of the through hole greater than that of an intermediate part of the through hole by performing overetching when the through hole is formed in a Si substrate by dry etching.
Of the patent documents described above, the technique disclosed in Patent Document 1 may make it difficult to form an insulation film on the inside surface of a through hole, and an enlarged intermediate part of the through hole makes the technique unfit to obtain a layout configuration with a narrow pitch by miniaturization. On the other hand, the technique disclosed in Patent Document 2 makes it easy to form an insulation film on the inside surface of a through hole. However, a large opening makes this technique also unfit to obtain a layout configuration with a narrow pitch by miniaturization.
Moreover, in the technique disclosed in Patent Document 3, overetching at the time of formation of a through hole is considered to become necessary for commercial mass production due to, for example, variations in the etching rate. In this case, as disclosed in Patent Document 4, a notch directed outward is formed between the bottom of the through hole and the insulation film. The notch in an insulation film interface part becomes a shadow for the opening, making it difficult to form the insulation film on the inside wall surface of the through hole. Moreover, since the amount of overetching varies depending on variations in the thickness of a Si substrate or variations in the etching rate, it is difficult to control the notch shape. Incidentally, U.S. Pat. No. 6,187,685 B1 (Patent Document 5) proposes a method for releasing electric charges at an insulation film interface part, the electric charges which cause a notch at the time of dry etching. However, this method does not promise the effect thereof in a laminated substrate such as a laminated chip because, in such a laminated substrate, a surface to which a pulse is applied is not a subject to be etched.